Analyzing interconnect structures

ABSTRACT

In one embodiment, an interconnect structure may be analyzed to determine electromagnetic characteristics of the structure by identifying structure seeds corresponding to the structure; modeling the structure seeds to obtain field patterns; and processing the field patterns to obtain the electromagnetic characteristics.

BACKGROUND

The invention relates to analyzing interconnect structures and morespecifically to analyzing such structures using modeling techniques.

Interconnect structures (also termed “interconnects”) are used toconnect circuitry and may be located either on or off of a semiconductordevice or chip. The accurate analysis of such structures is of greatimportance to high speed chip design since the performance ofinterconnects has impact on signal delay, signal decay, cross talk, andpower delivery. Such analysis becomes more important as the clockfrequency of microprocessors increases, heading to the 20 gigahertz(GHz) level in the 0.13 micron (μm) processing generation and beyond.However, the computational complexity of interconnects especiallyon-chip interconnects resulting from high conductor loss, strong skineffect, non-uniform dielectric, orthogonal layers, and large aspectratio prevents an efficient and rigorous analysis of large-scalethree-dimensional (3D) interconnects.

Two modeling methodologies for 3D on-chip interconnects have beenadopted. One manner of analyzing interconnect structures, particularly3-dimensional (3D) structures, is by extracting resistance (R),inductance (L), and capacitance (C) using computer aided design (CAD)tools and inputting the results into a circuit simulator. However, thisapproach is based on low frequency approximation, the validity of whichis questionable at high frequencies. Another manner of analyzing aninterconnect is to partition it into subcircuits and input the partsinto a full-wave solver and cascade each subcircuit to extract theoverall circuit behavior. However, this approach cannot modelelectromagnetic coupling correctly. To correctly do so, the entire 3Dstructure must be simulated instead of partitioning it first. However, a3D interconnect structure can involve billions of unknowns, which nocurrent computational resources can tolerate.

Thus a need exists to accurate and efficiently analyze interconnectstructures, such as large scale 3D structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram of a method in accordance with one embodimentof the present invention.

FIG. 2A is a transverse cross section view of an example interconnectstructure.

FIG. 2B is a top view of the example interconnect structure.

FIG. 2C is a partial side cross section view of the example interconnectstructure.

FIG. 3 is a block diagram of a system in accordance with one embodimentof the present invention.

DETAILED DESCRIPTION

In one embodiment of the present invention, an interconnect structure,such as a large scale, on-chip, 3D structure, is analyzed via full-wavemodeling. Such analyzing may obtain the electromagnetic fields withinthe structure and extract circuit parameters therefrom.

Such analysis of an interconnect structure may be performed inaccordance with the flow diagram set forth as FIG. 1, which is a flowdiagram of an example module for analysis of an interconnect structureaccording to one embodiment of the present invention.

Referring now to FIG. 1, in one embodiment using full-wave modeling, aninterconnect structure may be sliced into segments. Each segment has aconstant cross section. A plurality of unique structure seeds may beidentified from the interconnect structure undergoing analysis (block110). As used herein, the term “structure seed” means a two-dimensionalslice representing a unique three-dimensional geometric pattern of asegment of the interconnect structure. The number of unique structureseeds needed to represent an entire interconnect structure is dependenton the number of different geometric patterns of the interconnect, aswill be discussed in more detail below. Note that although the number ofsegments can be very large, the number of structure seeds is typicallyonly a few.

In one embodiment, electromagnetic behavior of each of the structureseeds next may be determined, for example, using a full waveelectromagnetic solver (block 120). Then mode matching may be performedat the junctions of the structure seeds to yield a final resultcorresponding to the electromagnetic characteristics of the interconnectstructure (block 130).

Referring now to FIG. 2A, shown is a transverse cross-section view of anexample interconnect structure 200, while FIGS. 2B and 2C show,respectively, a top view and a partial side cross-section view ofinterconnect structure 200. Arrow 201 in FIG. 2B indicates thelongitudinal direction of propagation through the interconnect structure200. Interconnect structure 200 includes six layers, namely first layer210, second layer 220, third layer 230, fourth layer 240, fifth layer250, and sixth layer 260. These layers may correspond to the six metallayers found in many semiconductor devices.

In this interconnect structure 200, signal lines are embedded in thefourth layer 240 and the sixth layer 260. Parallel returns lie in thesecond layer 220, and orthogonal returns reside in the first layer 210,third layer 230, and fifth layer 250. The orthogonal returns in thedifferent metal layers may be aligned or unaligned along thelongitudinal direction. The parallel returns may be randomly distributedin the transverse cross section.

In other embodiments, the lines of each of the layers may be signallines or return lines, and may be oriented in any desired manner. Whileshown having six layers, it is to be understood that interconnectstructure 200 may have more or fewer layers and/or lines in otherembodiments.

As discussed above, in one embodiment a set of unique structure seedsmay be identified. For interconnect structure 200, there may be at mosteight unique structure seeds, reflecting that the total number oforthogonal layers is three. In one embodiment, a three digit binarynumber may be used to describe the eight structure seeds, i.e, 000, 001,010, . . . , 110, and 111. In this three digit number, the first digitcorresponds to the fifth layer 250, the second digit corresponds to thethird layer 230, and the third digit corresponds to the first layer 210.The reason for selecting these layers (and a three digit binary number)to describe the structure seeds is that the other layers (i.e., secondlayer 220, fourth layer 240, and sixth layer 260) have constant crosssection throughout the structure.

In one embodiment, for each digit of the binary number, a zero value maydenote the absence of orthogonal returns in that layer, whereas a onevalue may denote the presence of such returns. If the orthogonal returnsare aligned in each layer (i.e., vertically aligned), the total numberof structure seeds needed to describe interconnect structure 200 is two.The first structure seed refers to the presence of all of the orthogonalreturns, while the second denotes their absence. The structure seeds maybe periodically repeated along the longitudinal direction of theinterconnect structure, thereby constructing the entire structure.

It is to be understood that in other embodiments, a differentcorrespondence between layers and digits may exist, and further that thedigit value may denote different meanings. More so, in other embodimentsdifferent schemes may be used to represent structure seeds.

After identification, the structure seeds may be used to further analyzethe interconnect structure. In one embodiment, full-wave modeling may beperformed on the structure seeds. While such full-wave modeling may beperformed in various ways and using various tools, in one embodiment,the full-wave modeling may be performed by invoking an electromagneticsolver, such as a frequency domain eigenvalue solver. In one embodiment,the solver may be performed via a CAD tool. Such a solver represents theoriginal wave propagation problem into a generalized eigenvalue problem.In one embodiment, the geometry and material description of theinterconnect structure may be used in performance of the solver. In suchan embodiment, the material description may include informationregarding the dielectric and conductive properties of the interconnectstructure.

In one embodiment, the solver may be arranged such that the eigenvaluesmay be the propagation constants of the modes that can be supported bythe interconnect structure, and the eigenvectors may correspond to thetransverse and longitudinal field distribution. That is, theeigenvectors may correspond to the field pattern in the structure seedsidentified as discussed above.

By employing the analytical feature of waves propagating along thelongitudinal direction in each segment, the solver may rigorously reducethe 3D discretization of the structure to two dimensions (2D), namelythe transverse cross section of the structure. Such transverse crosssection is shown, for example, in FIG. 2A. Despite a 2D discretization,both transverse and longitudinal fields within the structure aremodeled. The propagation characteristics and field pattern for eachstructure seed are returned. The field pattern is a superposition of allof the forward and backward propagation modes for that structure seed.Left unknown by the solver is how to weight these modes. Thus theunknown coefficients of each mode remain to be determined.

In one embodiment, post processing of the field patterns of thestructure seeds may next be performed to determine these coefficientsand obtain the solution of the original 3D problems. In one embodiment,the post processing may be accomplished via mode matching. Such modematching may be performed at the junctions of the structure seeds alongthe longitudinal direction. Mode matching essentially imposes thetangential continuity of the electric and magnetic fields at eachjunction.

In one embodiment, if an interconnect has n structure segments, and ineach segment there are m modes, the number of unknown coefficients is2×n×m. Mode matching yields 2m equations at each junction, thus giving a2×n×m matrix system for the entire structure. The matrix is sparse, andhas only 2×m nonzero elements in each row and can thus be efficientlysolved. This procedure also applies to the situation in which eachsegment has a different number of modes.

The solution of the matrix returns information regarding theelectromagnetic fields inside the interconnect structure under analysis.From this information, circuit parameters may be readily extracted. Inone embodiment, the circuit parameters may be full-wave equivalentcircuit parameters including resistivity (R), capacitance (C),inductance (L), and conductance (G) (collectively the full-wave RLGC).Additionally, scattering parameters (S-parameters), which are reflectionand transmission coefficients between incident and reflection waves, maybe obtained. In addition, field and current distribution of theinterconnect may be obtained.

Thus according to one embodiment, full-wave modeling of 3D interconnectsmay be performed by identifying and obtaining solutions to a pluralityof 2D problems. The solution of these 2D problems may then be postprocessed to obtain the solution of the original 3D problems. Despitethe complexity of the 3D interconnect, the full-wave solution may beaccomplished by only using 2D-like processor time and memory. In sodoing, rigorous fast analysis of the interconnect structure may beaccomplished without introducing any approximation.

While described above with regard to an on-chip interconnect structure,it is understood that embodiments of the present invention may be usedto analyze off-chip structures, optical fibers, and other dielectric andmetallic waveguides.

Embodiments may be implemented in a computer program, for example, afull-wave interconnect simulator implemented in a CAD tool. As such,these embodiments may be stored on a storage medium having storedthereon instructions which can be used to program a computer system toperform the embodiments. The storage medium may include, but is notlimited to, any type of disk including floppy disks, optical disks,compact disk read-only memories (CD-ROMs), compact disk rewritables(CD-RWs), and magneto-optical disks, semiconductor devices such asread-only memories (ROMs), random access memories (RAMs), erasableprogrammable read-only memories (EPROMs), electrically erasableprogrammable read-only memories (EEPROMs), magnetic or optical cards, orany type of media suitable for storing electronic instructions.Similarly, embodiments may be implemented as software modules executedby a programmable control device. A programmable control device may be acomputer processor or a custom designed state machine. Custom designedstate machines may be embodied in a hardware device such as a printedcircuit board having discrete logic, integrated circuits, or speciallydesigned application specific integrated circuits (ASICs).

Example embodiments may be implemented in software for execution by asuitable data processing system configured with a suitable combinationof hardware devices. FIG. 3 is a block diagram of a representative dataprocessing system, namely computer system 300 with which embodiments ofthe invention may be used.

Now referring to FIG. 3, in one embodiment, computer system 300 includesa processor 310, which may include a general-purpose or special-purposeprocessor such as a microprocessor, microcontroller, ASIC, aprogrammable gate array (PGA), and the like. As used herein, the term“computer system” may refer to any type of processor-based system, suchas a desktop computer, a server computer, a laptop computer, anappliance or set-top box, or the like.

The processor 310 may be coupled over a host bus 315 to a memory hub 320in one embodiment, which may be coupled to a system memory 330 via amemory bus 325. The memory hub 320 may also be coupled over an AdvancedGraphics Port (AGP) bus 333 to a video controller 335, which may becoupled to a display 337. The AGP bus 333 may conform to the AcceleratedGraphics Port Interface Specification, Revision 2.0, published May 4,1998, by Intel Corporation, Santa Clara, Calif.

The memory hub 320 may also be coupled (via a hub link 338) to aninput/output (I/O) hub 340 that is coupled to a input/output (I/O)expansion bus 342 and a Peripheral Component Interconnect (PCI) bus 344,as defined by the PCI Local Bus Specification, Production Version,Revision 2.1 dated in June 1995. The I/O expansion bus 342 may becoupled to an I/O controller 346 that controls access to one or more I/Odevices. As shown in FIG. 3, these devices may include in one embodimentstorage devices, such as a floppy disk drive 350 and input devices, suchas keyboard 352 and mouse 354. The I/O hub 340 may also be coupled to,for example, a hard disk drive 356 and a compact disc (CD) drive 358, asshown in FIG. 3. It is to be understood that other storage media mayalso be included in the system.

In an alternate embodiment, the I/O controller 346 may be integratedinto the I/O hub 340, as may other control functions. The PCI bus 344may also be coupled to various components including, for example, anetwork controller 360 that is coupled to a network port (not shown).

Additional devices may be coupled to the I/O expansion bus 342 and thePCI bus 344, such as an input/output control circuit coupled to aparallel port, serial port, a non-volatile memory, and the like.

Although the description makes reference to specific components of thesystem 300, it is contemplated that numerous modifications andvariations of the described and illustrated embodiments may be possible.For example, instead of memory and I/O hubs, a host bridge controllerand system bridge controller may provide equivalent functions. Inaddition, any of a number of bus protocols may be implemented.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of this present invention.

1. A method comprising: identifying a first seed and a second seed eachcorresponding to a three dimensional interconnect structure having aplurality of layers, each seed including a unique two dimensional crosssection of the three dimensional interconnect structure; forming a firsttwo dimensional model of the first seed in the frequency domain toobtain a first two dimensional electromagnetic field; forming a secondtwo dimensional model of the second seed in the frequency domain toobtain a second two dimensional electromagnetic field; determining afirst mode of operation and a second mode of operation for the firstseed; determining a third mode of operation and a fourth mode ofoperation for the second seed; mode matching to obtain a first weightingcoefficient for the first mode, a second weighting coefficient for thesecond mode, a third weighting coefficient for the third mode, and afourth weighting coefficient for the fourth mode; forming a threedimensional model based on the first two dimensional electromagneticfield, the second two dimensional electromagnetic field, the firstweighting coefficient, the second weighting coefficient, the thirdweighting coefficient, and the fourth weighting coefficient.
 2. Themethod of claim 1, wherein the first mode and the second mode are eachforward propagation modes and the third mode and the fourth modes areeach backward propagation modes.